TSMC has actually exposed some extra information about its upcoming N2 and N2P procedure innovation at its European Innovation Seminar 2023. Both production nodes are being established with high-performance computing (HPC) in mind, so, they include a variety of improvements created particularly to enhance efficiency. On the other hand, provided the performance-efficiency focus that a lot of chips intend to surpass, low-power applications will likewise benefit from TSMC’s N2 nodes as they will naturally enhance performance-per-watt compared to predecessors.
” N2 is a fantastic suitable for the energy effective computing paradigm that we remain in today,” stated Yujun Li, TSMC’s director of organization advancement who supervises of the foundry’s High Efficiency Computing Organization Department, at the business’s European Innovation Seminar 2023. “The speed and power benefits of N2 over N3 over the whole voltage supply varies as revealed is really constant, making it ideal for both low-power and high-performance applications at the exact same time.”
TSMC’s N2 production node — the foundry’s very first production nodes to utilize nanosheet gate-all-around (GAAFET) transistors– assures to increase transistor efficiency by 10-15% at the exact same power and intricacy, or lower power use by 25-30% at the exact same clock speed and transistor count. Power shipment is among the corner stones when it concerns enhancing transistor efficiency and TSMC’s N2 and N2P production procedures present numerous interconnects– associated developments to squeeze some extra efficiency. In addition, N2P generates behind power rail to enhance power shipment and pass away location.
Among the developments that N2 gives the table is super-high-performance metal-insulator-metal (SHPMIM) capacitor to boost power supply stability and assist in on-chip decoupling. TSMC states that the brand-new SHPMIM capacitor provides over 2X greater capability density compared to its super-high-density metal-insulator-metal (SHDMIM) capacitor presented numerous years ago for HPC (which increased capacitance by 4X when compared to previous-generation HDMIM). The brand-new SHPMIM likewise minimizes Rs sheet resistance (Ohm/square) by 50% compared to SHDMIM in addition to Rc by means of resistance by 50% compared to SHDMIM.
Yet another method to decrease resistance in the power shipment network has actually been to rearchitect the redistribution layer (RDL). Beginning with its N2 procedure innovation, TSMC will utilize a copper RDL rather of today’s aluminum RDL. A copper RDL will supply a comparable RDL pitch, however will decrease sheet resistance by 30% in addition to lowered by means of resistance by 60%.
Both SHPMIM and Cu RDL become part of TSMC’s N2 innovation that is forecasted to be utilized for high volume production (HVM) in the 2nd half 2025 (probably really late in 2025).
Decoupling Power and I/O Circuitry
Making use of a behind power shipment network (PDN) is a yet another significant enhancement that will be included by N2P. General benefits of behind power rail are popular: by separating I/O and power circuitry by moving power rails to the back, it is possible to make power wires thicker and for that reason decrease by means of resistances in the back-end-of-line (BEOL), which assures to enhance efficiency and reduce power usage. Likewise, decoupling I/O and power wires permits to diminish reasoning location, which indicates lower expenses.
At its Innovation Seminar 2023 the business exposed that behind PDN of its N2P will make it possible for 10% to 12% greater efficiency by lowering IR sag and enhancing signaling, in addition to lowering the reasoning location by 10% to 15%. Now, obviously, such benefits will be more apparent in high-performance CPUs and GPUs that have thick power shipment network and for that reason moving it to the back makes a fantastic sense for them.
Behind PDN belongs of TSMC’s N2P fabrication innovation that will get in HVM in late 2026 or early 2027.